1. Field of the Invention
The present invention relates to a decoder checking circuit for checking a decoder used for a semiconductor memory such as a static Random Access Memory (SRAM), a dynamic RAM (DRAM) or the like.
2. Description of the Related Art
Circuit testing has been very important together with the increased density of semiconductor memories such as dynamic RAMs in order to ensure the good reliability. Various proposals have been offered to simplify the testing system. A semiconductor memory testing technology was disclosed in the paper entitled, "Incorporated Self-Test Memory (1) - Applications To DRAM", written by Takada and Shimada et al, pages 5-327, in the 1989 Spring Domestic Meeting of Electron Data Communication Society.
FIG. 2 is a block diagram illustrating an arrangement of conventional self-test type dynamic RAM.
In FIG. 2, a memory cell array 1 has a plurality of memory cells. The memory cell array 1 also is connected to a column decoder 2 for decoding an address signal AD to select memory cells associated with a column line, and a row decoder 3 for selecting memory cells associated with a row line. Further, the memory cell array 1 is connected to the column decoder 2, the row decoder 3, the input/output bus 4.
Such a conventional RAM device has also a self-test function constituted by a micro read-only memory (ROM) 10, a test control circuit 11 for switching selectively to a normal memory operation mode and a self-test mode in response to a switching signal TE, and a pattern comparing circuit 12.
The micro ROM 10 stores a test pattern generating and comparing program for carrying out a marching test and a checker board test in a form of a microcode.
This dynamic RAM switches its operation mode between the normal memory operation mode and the self-test mode in response to the switching signal TE. In the normal memory operation mode, the address signal AD is decoded by the column decoder 2 and the row decoder 3. Memory cells in the memory cell array 1 are selected in accordance with the result of the decoding, whereby data are written into and read from the selected memory cells through the input/output bus 4.
In a memory self-test mode, after the self-test function is initialized in accordance with a test pattern stored in the micro ROM 10, date are written in the memory cells of the memory cell array 1. Then the data thus written are read and compared with an expected value by the pattern comparing circuit 12. The test result representing coincidence or non-coincidence is outputted. With the result of this test, it is possible to test whether the operating condition of the entire dynamic RAM including the column decoder 2, the row decoder 3 and the memory cell array 1 is normal or abnormal.
However, the above-mentioned conventional self-test type dynamic RAM has given the following problems:
In the conventional self-test system, the test pattern generating and comparing program is stored in the micro ROM 10 in a form of a micro code, and the quality of the entire dynamic RAM is determined in accordance with the test pattern.
In order to improve the reliability of the dynamic RAM, it is required to test the quality of each of circuits in the dynamic RAM and to analyze the operational condition of each circuit. Particularly, in a semiconductor memory, it is required to individually check the memory cell array 1, the column and row decoders 2, 3 which are a main portion of the semiconductor memory. It is relatively convenient to check the quality of the memory cell array 1.
However, in order to test the column decoder 2 and the row decoder 3, a specific bit pattern has to be mapped on a memory plane, as in a marching test or a checker board test. Accordingly, a large test pattern is required. Further, the performance of this test pattern for testing the column decoder 2 and the row decoder 3 requires a very long period of test time. Therefore, it has been difficult to solve easily such a problem on the decoder testing.